Teledyne SP Devices

TEMP: ADX - Time-interleaving Technology for Analog-to-Digital Converters

Limitations in Analog-to-digital Conversion
Click to view gallery Achievable vertical resolution and spurious performance of analog-to-digital converters (ADCs) are tightly connected to the maximum sampling frequency of the device. This is an highly undesireble situation as it leaves designers constrained in their choice of vertical resolution, sampling rate, or both. As an example, in January 2014 commercially available 16-bit monolithic, single-core (non-interleaved) ADCs are limited to 250 MS/s sampling rate while 14-bit ADCs offers 400 - 500 MS/s. The corresponding number for a single-core 12-bit ADC design is 1500 MS/s.

Addressing Sampling Rate Constraints
adx_thumbnail_gsMany applications benefit from higher sampling rate for a given vertical resolution and time-interleaved ADCs (TIADCs) is a well-recognized approach to achieving this. The basic principle is simple to comprehend - the same analog input is connected to an array of ADCs where each individual ADC-core is fed a phase-skewed sampling clock relative to the other ADCs. The technique can be applied either to multiple discrete ADCs mounted on a printed-circuit board (PCB) or internally inside an ADC component where several ADC cores then reside on the same die.

Challenges with Time-Interleaving
adx_thumbnailInternally interleaved monolithic ADCs are becoming more common, and many of today's commercial high-performance ADCs are based on this approach. However, the internal structure of these components introduces analog mismatch errors which degrade performance unless calibrated or corrected. Mismatch error estimation and correction accuracy is crucial and becomes increasingly important with higher resolution ADCs. As an example the variation after correction must be less than 0.01% in order to maintain typical performance in an interleaved 14‑bit ADC!

The ADX Difference
adx_thumbnailAt SP Devices we have been conducting research in time-interleaving since 1998 and we commercialized ADX in 2004. Through years of continuous R&D we have strived for perfection in time-interleaving technology, and we are convinced that ADX is the most comprehensive and highest performing solution available today. The technology has been used both with discrete ADCs as well as embedded in ASICs, and we are proud to have had ADX endorsed by companies such as Texas Instruments, National Semiconductor, Intersil, e2v, and LeCroy.

Implementation Alternatives
adx_thumbnailADX is a purely digital IP-block that can be implemented in either FPGAs, ASICs, or software. Existing off-the-shelf FPGA firmware images are available for a set of pre-defined performance specifications and ASIC implementations can be done for different digital design library/process node targets. The technology is generic and can be used with any ADC, but modifications/optimizations may be beneficial in achieving specific performance goals. ADX provides self-learning continuous background calibration/correction without the need for calibration signals or post‑production trimming.


  • "The technical and intellectual support from the team at Teledyne SP Devices has been playing an important role in our research."

    Associate Professor at Hong Kong University (HKU)
    who has implemented a system supporting line scan rates of 10M lines/s

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    prof. Jakub Čížek, Department of Low Temperature Physics at Charles University, Prague

  • "The ADQ7DC digitizer is the best device of this type available on the market with high sampling rate, wide analog bandwidth, quality and stability of signal acquisition. A professional team of the SP Devices engineers ensure support and quick response to the inquiries."

    M. Sc. Grzegorz Nitecki, Faculty of Electronics, Military Academy of Technology, Warsaw, Poland

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