Ultra-fast AI inference at 10 GSPS detects particle pile-up in real time
Figure 1. The SIS18 tunnel at GSI Helmholtzzentrum für Schwerionenforschung in Darmstadt, Germany. (Bild: A. Zschau, GSI/FAIR)
Introduction
How FPGA-based AI inference at 10 giga-samples-per-second (GSPS) on the Teledyne ADQ35 enables
reliable and accurate particle localization, in real time, with sub-microsecond latency, and sub-nanosecond time resolution, even at high particle rates with significant signal overlap.
Particle accelerators deliver precisely controlled particle beams for scientific experiments, materials research, and medical applications. To ensure this,
each particle in the beam has to be localized in real time while the accelerator is operating, which is a major task in beam instrumentation for particle accelerators.
A detector is placed into the beam, which emits a pulse for each particle passing through it. Figure 2 shows an example: the graph shows how the signal from the detector changes over time when a particle passes through.
Figure 2. The pulse generated when a particle hits the detector. Illustrative example, not measured data.
Challenge: Pile-Up
If multiple particles pass through the detector within a short time interval, the pulses overlap and the
detector response can become nonlinear. This phenomenon of overlapping pulses is called
“pile-up.” The likelihood of pile-ups increases with higher particle rates.
Traditional methods such as multi-threshold detection or local maxima search struggle
and often fail to detect particles when pile-up occurs. This leads to undercounting, which can be detrimental for downstream experiments.
Figure 3 shows examples of such pile-up events. Each example shows the signal produced by the detector when three particles arrive at almost the same time. The green dotted lines show the arrival times of each particle. The detector can behave nonlinearly when pile-up occurs, and it becomes difficult to extract individual pulses from the piled-up signal.
Figure 3. Examples where three particles arrive at almost the same time, resulting in pile-up. The green dotted lines show the arrival times of each particle. Illustrative examples, not measured data.
Highlights
- Localizing
each individual particle traveling at relativistic speeds, in real time.
-
300 ns inference latency at 10 GSPS — over 100 Gbit/s of data processed in real time.
- Uses less than
15% of DSP and
6% of LUT resources on the FPGA, leaving headroom for bigger models.
-
Resolves pile-up reliably, so particle rates no longer need to be reduced to avoid it.
AI-Based Signal Processing on FPGA
This case study shows how to deploy AI to overcome these limitations within strict real-time constraints. Our implementation is
processing over 100 gigabits of data per second with a latency of just 300 nanoseconds.
This case study was conducted as part of doctoral research at Fulda University of Applied Sciences in collaboration with GSI Helmholtzzentrum für Schwerionenforschung. The work is published in [1] and [2].
To address this challenge, a convolutional neural network (CNN) was developed and trained on labeled data. It was then implemented directly on FPGA hardware using a toolchain which is now the technical basis of
UFAIRA.
The AI model
localizes each individual pulse, even when pile-up occurs, extracting both particle count and time-of-arrival information in real time. This enables accurate reconstruction of events even at very high rates.
The CNN FPGA implementation processes the data inline and ensures
deterministic latency, which is very important for real-time applications.
Figure 4. Three particles arriving almost simultaneously. Green dotted lines mark true positions; black dots show the CNN's predicted positions. Illustrative example, not measured data.
Implementation on the ADQ35 Digitizer
The solution is realized using the Teledyne SP Devices ADQ35 high-speed digitizer, with sampling rates up to 10 GSPS and an onboard AMD Kintex UltraScale KU115 FPGA. This provides plenty of computational resources for real-time AI inference directly on the digitizer.
By processing the data directly on the digitizer, the system
avoids data transfer bottlenecks and enables sub-microsecond latency operation.
Using a toolchain for FPGA-optimized hardware-aware training and implementation of the CNN in FPGA fabric, the implemented CNN is able to process
32 samples in parallel at 312.5 MHz, leading to 10 GSPS, with a low and deterministic latency and high accuracy.
Results and Benefits
The implemented CNN achieves a latency of just
300 nanoseconds, processing
120 gigabits per second (10 GSPS, with 12 bits per sample).
It uses less than
15% of the available DSP resources and less than
6% of available LUT reources on the FPGA, thereby leaving plenty of space for even bigger models or even higher throughput requirements. This demonstrates that advanced machine learning models can operate efficiently within the constraints of high-speed hardware.
The AI-based approach significantly improves performance under pile-up conditions and
outperforms all traditional methods. The CNN localizes individual pulses in pile-up events with such reliability that pile-up events no longer have to be avoided by reducing the particle rate.
As this solution solves the pile-up problem, it allows the system to run at
much higher particle rates without requiring changes to the detector hardware itself.
When Does AI Help in High-Speed Real-Time Data Processing?
Many potential users are not aware of when AI can provide value in data processing systems. Based on this example, AI becomes particularly relevant when:
- Multiple events occur within the same timespan, producing a superimposed signal (like pile-up)
- The signal processing is too complex for traditional methods (learned function approximation)
- The signal shapes vary due to real-world effects (drift, noise, nonlinearity)
In these scenarios,
AI models can learn complex signal behavior and extract information that is difficult or impossible to recover using traditional methods in real time.
Broader Use Cases
The approach demonstrated here is broadly applicable across many high-speed data domains that require real-time processing, including:
- Channel estimation in RF systems
- High-frequency trading
- Network intrusion detection
- Image processing for autonomous systems
All of these examples need inline processing of the data with low latency.
UFAIRA
The methods and toolchain used in this research are now the basis for UFAIRA, a company building customized FPGA-based AI accelerators for real-time inference, founded in 2026 as a spinout from the doctoral research described above.
UFAIRA was not a party to that work, and GSI is not a customer of UFAIRA. Learn more at
https://ufaira.eu.
References
[1] T. Habermann, M. Kumm, and R. Singh, "Application of convolutional neural networks for pile-up correction in single particle counting", in Proc. IBIC 2025, Liverpool, UK, Sep. 2025, paper MOPCO36, pp. 152-155. doi:10.18429/JACoW-IBIC2025-MOPCO36
[2] R. Singh, T. Habermann, M. Kumm, and P. Boutachkov, "CNN-based arrival time determination in piled-up particle counter signals", presented at IPAC'26, Deauville, France, May 2026, paper WEP6047, pp. 3028-3031, to be published.
