ADX - ADC Interleaving IP
ADX is an interleaving post-correction digital IP with extreme performance. It removes distortions related to interleaving such as time-skew, offset- and gain- errors. Corrections are made transparently and in real time without any need of specific calibration signals. The IP is available in the delivery formats software IP, FPGA IP and silicon IP. For evaluation of the technology or examples of ADC array system design with the IP, SP Devices offers EVM hardware for different target specifications.
For a short overview on time-interleaving and ADX please view our recorded webinar below.
ADX Design Kit
The ADX Design Kits are the packages to use for in-design of the ADX IP on FPGAs. The kits contain all necessary contents to provide an easy integration.
The ADX EVMs (EValuation Modules) are hardware platforms with specific ADC arrays interleaved in different configurations. Use the EVM to evaluate the ADX technology and ADX Design kit for implementing ADX into the target system. Combined with an ADX license, the EVM can also be used as a direct solution to a system's AD conversion. Customization of the EVMs for target systems is possible.
For the production of systems with the ADX interleaving IP, each individual system must be equipped with a run-time license. Licenses for FPGA IP is supplied on a license EEPROM device (1-wire).
ADX Design services
SP Devices offer design services in both the analogue and digital domain to support system development with the ADX IP cores. Click here to read more.