Through collaboration between Intersil and SP Devices, this reference design offers 12-bit resolution and 2 GSPS sample rate. It features four low-power ISLA112P50, 12-bit 500 MSPS ADCs from Intersil in combination with SP Devices' interleaving IP ADX. At 190 MHz input frequency the signal-to-noise ratio (SNR) is 65.5 dB and the spurious free dynamic range (SFDR) is 82 dBc - both figures significantly better than available stand-alone 2 GSPS solutions according to Intersil. The SNR performance is maintained over the entire analog input bandwidth whereas the SFDR is superior up to 500 MHz compared to similar solutions. Given these outstanding performance figures, the reference design serves as an excellent starting point for new designs within various application areas. The board has a USB 2.0 port for communication with the FPGA and an on-board memory of 64 kSamples. Setup and control of the evaluation board is made by the included software ADCaptureLab. The software contains useful analysis tools such as time series and FFT plots to facilitate the evaluation of the IP-block for the target application. Further information is available on Intersils' website here (external link).

The ADS5474-ADX4 is among the fastest 14-bit ADC solutions available and offers giga sample per second (GSPS) capture. The evaluation module (EVM) employs four 14-bit, 400 MSPS ADS5474 ADCs from Texas Instruments, and operates in a time-interleaved fashion to realize a total sample rate of 1.6 GSPS.

With its exceptional dynamic performance, such as 88 dBc spurious-free dynamic range (SFDR), the EVM is an excellent choice for RF sampling, IF sampling, Software Defined Radio and similar applications. The outputs of the four ADCs are connected to a Xilinx Virtex 5 FPGA which incorporates SP Devices' proprietary interleaving IP, ADX. The IP continuously analyzes and corrects the ADCs' outputs, thereby automatically removing the otherwise occurring aliasing distortion and tones arising from gain, offset and time skew mismatch errors. Due to the frequency and temperature dependent nature of the mismatch errors, the continuous background correction is crucial to ensuring the highest achievable performance at all time and under all circumstances.

Time-interleaving of analog-to-digital converters (ADCs) is a way to increase the overall system sampling rate by using several ADCs in parallel. The challenge is to handle the mismatch between the individual ADCs, especially at higher frequencies. With its unique self-learning and high-resolution capabilities, SP Device's ADX technology offers previously unseen performance. Corrections are made transparently and in real-time without any need for calibration signals or idle time slots during which to perform calibration. The mismatch correction algorithm supports a resolution of up to 16 bits, with a preserved SFDR of up to 95 dB, depending on the properties of the specific ADC array.

We help our customers to improve competitiveness regardless of where they are positioned in the value chain. The offering from SP Devices covers the complete range from Silicon Manufacturers to System Integrators. SP Device's products are available as Silicon IP, FPGA IP, reference designs, and complete digitizer boards.

The ADX interleaving technology is available as silicon IP for chip manufacturers and semiconductor companies who need to increase ADC sampling speed. ADX is also available as FPGA IP, targeting the market of system suppliers, digitizer companies, and T&M companies.

For customers who do not want to design their own digitizer solution, SP Devices offers both off-the-shelf digitizer solutions as well as customized digitizers.