Data Acquisition Signal Processing IP

Processing in the FPGA result in the most compact system. There are two main reasons for that: Advanced FPGAs are required on the ADQ because of the high data rate. These FPGAs are powerful computational resources. Custom processing in the FPGA use the available resources efficiently and off-load the host PC

Baseline (DC level) drift caused by temperature fluctuations and other factors can result in false readings and/or performance degradation in time-domain pulse applications. Furthermore pattern noise from time-interleaved ADCs makes the situation even worse.

Time‑interleaving of analog‑to‑digital converters (ADCs) is a way to increase the overall system sample rate by using several ADCs in parallel. The challenge is to handle the mismatch between the individual ADCs, especially at higher frequencies.

Digital post‑linearization increases the effective resolution of analog‑to‑digital conversions. The ADL linearization technology developed by SP Devices suppresses performance-limiting non‑linearities of ADCs and the preceding signal path (amplifiers, filters, buffers, etc.).

Digital I/Q imbalance correction match the in-phase and quadrature signal paths in radio architectures employing complex demodulators such as direct down-conversion receivers. The distortion due to signal path imbalances is attenuated effectively over a large bandwidth.