The data reduction can be achieved in many ways, for example:
Triggered acquisition of a user-defined number of consecutive samples
(so-called records). Data reduction is achieved by only transferring the
records while the rest of the data is discarded. This functionality is
supported by our firmware options FWDAQ and FWPD.
In frequency-domain applications, it is common with digital down
conversion that combines filtering and decimation to achieve data
reduction. This is supported by FWSDR (for ADQ14) and FW2DDC (for ADQ7).
Application-specific data reduction based on known information about the
acquired signal. For example real-time averaging of known repetitive
signals, or extracting signal characteristics from time-domain pulses.
This is supported by the firmware options above as well as FWATD.
Custom data reduction can be implemented using the firmware development
kit. This offers full flexibility and can either be implemented by the
customer or by utilizing design services offered to OEM customers.
Massive data reduction can be achieved via the FPGA pre-processing. One
such example is the use of real-time waveform averaging on ADQ7 using
FWATD. This combination has been used by for example mass spectrometry
customers to reduce the output rate from 20 Gbyte/s to 40 Mbyte/s - a
reduction of 500 times without loss of signal properties/characteristics!
FPGA pre-processing, therefore, allows for maximum flexibility in the
mechanical design. Form factors such as USB 3.0 with seemingly limiting
data transfer rates of a few hundred Mbyte/s can still be fully utilized
due to the data reduction. This in turn offers additional benefits such as
locating the digitizer close to the detector in order to minimize